The semiconductor industry continues to present a need for the development of new, low dielectric constant (k) materials to foster improved microprocessor performance. In particular, there is a strong drive to reduce the dielectric constant of interlayer dielectric (ILD) materials, such as those existing between metal lines. It has been recognized that the speed of propagation of interconnect signals significantly impacts overall circuit speed in microprocessors, particularly as feature sizes are reduced and the number of devices per unit area is increased. With the reduced size of microprocessor features, interconnect signals may travel faster through conductors due to a concomitant reduction in resistance-capacitance (RC) delays. The approach of introducing porosity to dielectric materials to decrease their k has been adopted to provide a pathway for generational extendibility. Porous ultra low-k (ULK) dielectrics have enabled capacitance reduction in advanced silicon complementary metal-oxide semiconductor (CMOS) back end of line (BEOL) structures. However, while increasing porosity may lower the dielectric constant, other properties of dielectric materials—such as ULK stiffness, fracture resistance, and interfacial adhesion—can be negatively impacted due to a decrease in density and network-connectivity. Likewise, while high levels of porosity may assist in achieving, for example, k values of 2.4 or lower, such porosity can also result in dielectric material damage or loss during plasma exposures (such as reactive ion etch (RIE), strip, or dielectric barrier etch) and wet cleans (such as post-RIE dilute hydrofluoric acid (DHF) cleans).